1Field of the Invention
The present invention generally relates to the design and testing of integrated circuits, and more particularly to a method and system for testing an array of electronic devices.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements grouped to perform a logic function. Cell types include, for example, core cells, scan cells and input/output (I/O) cells. Each of the cells of an IC may have one or more pins, each of which in turn may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip. For more complex designs, there are typically at least four distinct layers of conducting media available for routing, such as a polysilicon layer and three metal layers (metal-1, metal-2, and metal-3). The polysilicon layer, metal-1, metal-2, and metal-3 are all used for vertical and/or horizontal routing.
An IC chip is fabricated by first conceiving the logical circuit description, and then converting that logical description into a physical description, or geometric layout. This process is usually carried out using a “netlist,” which is a record of all of the nets, or interconnections, between the cell pins. A layout typically consists of a set of planar geometric shapes in several layers. The layout is then checked to ensure that it meets all of the design requirements, particularly timing requirements. The result is a set of design files known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator. During fabrication, these masks are used to pattern one or more dies on a silicon wafer using a sequence of photolithographic steps. The process of converting the specifications of an electrical circuit into a layout is called the physical design.
Cell placement in semiconductor fabrication involves a determination of where particular cells should optimally (or near-optimally) be located on the surface of a integrated circuit device. Due to the large number of components and the details required by the fabrication process for very large scale integrated (VLSI) devices, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use computer-aided design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance. Several different programming languages have been created for electronic design automation (EDA), including Verilog, VHDL and TDML. A typical EDA system receives one or more high level behavioral descriptions of an IC device, and translates this high level design language description into netlists of various levels of abstraction.
Faster performance and predictability of responses are elements of interest in circuit designs. As process technology scales to the deep-submicron (DSM) regime, it is becoming increasingly important for the performance and reliability of IC chips and systems to understand how variations in process parameters affect the operation of an electronic device or circuit. A designer needs to model responses such as current flow with changes in voltage for transistors (I-V curves), or resistance/capacitance measurements for wiring. Device testing may further include leakage measurements across a gate, to indirectly assess the quality of an oxide material and identify potential flaws like pin holes or edge defects. Some devices such as static random-access memory (SRAM) require testing the memory elements with random fluctuations in threshold voltages to better characterize the circuit. Devices should also be stress tested, i.e., under different conditions such as varying temperatures. It is also useful to understand how spatial variations (i.e., devices located in different dies on a single wafer) can affect process parameters.
One example of a circuit used for such testing of an array of devices is shown in FIG. 1. The devices under test (DUTs) in circuit 2 are transistors, three of which 4, 6, 8 are shown arranged in a row. Circuit 1 can be replicated for other rows which together form an array of DUTs. Each DUT receives three voltage signals, a drain voltage VD, a gate voltage VG, and a source voltage VS. These voltage signals are fed by three respective operational amplifiers 10, 12, 14. The amplitude of the voltage signals may be selectively controlled using respective digital-to-analog converters (DACs) 16, 18, 20 each of which has an N-bit control input. The terminal end of the voltage supply rail 22 is connected to measurement circuitry, e.g., current sensors. Current output for each pin set in the row is monitored as the voltages are varied to establish I-V curves for the devices.
While the outputs of circuit 2 provide a fair basis to characterize the response of the devices, the measurements are not completely accurate since they fail to take into consideration loading effects on signal transmission. Even metal wires have a very small resistance, represented in FIG. 1 as resistor symbols along sections of the transmission lines. This resistance (as well as capacitance) affects the propagation of signals in the wires. These loading effects can vary with wire length and environmental parameters such as temperature. In order to have a truly precise measurement, it is necessary to know the exact value of the test parameter applied to the device (e.g., voltage). While the loading effects can be estimated based on theoretical values or manufacturing specifications, physical analysis of resistance effects for different wiring indicates that the actual values within a cell can vary considerably from an expected norm. Calibration of the measurement circuitry does not compensate for variations in the loading effects.
There are many circuit designs adapted to sense or supply an exact voltage in a circuit. U.S. Pat. No. 3,818,274 describes a remote sensing voltage clamping circuit, that clamps a power source output level to prevent overvoltage levels at a remote load. That design uses a high impedance sensing lead and a detector-clamping circuit coupled intermediate the sending lead and the power source. U.S. Pat. No. 4,169,243 discloses a remote sensing apparatus used with a measurement device such as a strain gauge. The apparatus uses two operational amplifiers to cancel errors in the output voltage due to voltage drops in three lead wires. U.S. Pat. No. 5,977,757 teaches a power supply having automatic voltage sensing. The power supply generates a regulated voltage in response to an input voltage and an error signal, and the error signal is generated by a sensing circuit having a high input impedance differential amplifier with inputs coupled to voltage sense terminals. U.S. Pat. No. 5,999,002 shows a contact resistance check circuit that verifies when a sufficient electrical connection is established between a source and a sense lead of a Kelvin connection. An input pulse to the sense probe is altered in related to the contact resistance to produce a check pulse. A comparator generates a fault indication signal if the voltage of a check pulse exceeds a threshold voltage.
These sensing techniques basically apply a voltage and sense the actual voltage with a high impedance node. They all use discrete components, that is, separate circuit structures, which facilitates remote sensing, but there are problems with applying these techniques to testing of electronic devices. Because of their discrete nature, it is difficult to implement these designs in a single integrated circuit. Also, none of these techniques can be rasterized, i.e., applied to an array of columns and rows of devices. It is useful to be able to have an array structure for testing to measure spatial variations in devices/circuits.
In light of the foregoing, it would be desirable to devise an improved method of applying a known voltage to a testing device/circuit which takes loading effects into consideration. It would be further advantageous if the method could be implemented in a geometric matrix (row/column array) of devices/circuits under test.